This scenario highlights a critical architectural transition point within the Pure Storage FlashArray product line. The arrays utilize dedicated NVRAM modules to safely ingest and acknowledge incoming writes before destaging them to the capacity flash drives.
On the lower to mid-range models (such as the //X10, //X20, and //X50), the system requires only two NVRAM modules to maintain a highly available, mirrored write cache. These are physically installed in the central chassis slots NVB0 and NVB1. However, the higher-end, performance-heavy models (such as the
//X70 and //X90) boast significantly more processing power and ingest bandwidth. To support these massive workloads without creating a cache bottleneck, the architecture mandates four NVRAM modules, filling slots NVB0, NVB1, NVB2, and NVB3.
Therefore, when performing an inter-generational, cross-model Hardware Non-Disruptive Upgrade (HWNDU) from an //X50 to an //X70 , the Implementation Engineer is traversing that architectural boundary.
While performing the controller swaps, the engineer is strictly required to install two additional, newly shipped NVRAM modules into the previously empty bays NVB2 and NVB3. If they fail to add these modules, the new //X70 controllers will detect a cache hardware deficiency and refuse to initialize, halting the upgrade process. Options B, C, and D do not cross this 2-to-4 NVRAM threshold.